2D Carrier Nanometrology Lab

Scanning Capacitance Microscopy (SCM) Lab

Model nanoscale tip-sample MOS differential capacitance (dC/dV), lock-in carrier polarity phase detection, sub-nanometer metallurgical junction delineation, and 20-year semiconductor fab tool DCF.

Ultra-scaled 2nm gate-all-around nanosheet transistor. Requires sub-2nm spatial resolution to delineate lateral source/drain extension under the spacer.

SCM Tool & Semiconductor Controls

1.0e+20 cm⁻³
10¹⁷ cm⁻³ 10¹⁹ cm⁻³ 5×10²⁰ cm⁻³
2.0e+18 cm⁻³
10¹⁵ cm⁻³ 10¹⁷ cm⁻³ 5×10¹⁹ cm⁻³
1.2 nm/dec
0.6 nm/dec (Ultra-abrupt) 50 nm/dec
6 nm
4 nm (Sharp Diamond/PtIr) 30 nm
0.8 nm
0.5 nm (UV-ozone native) 5.0 nm
0.5 V
0.2 V (High resolution) 2.5 V
0.0 V
-1.5 V 0.0 V +1.5 V
1.20 GHz
0.8 GHz 1.5 GHz

Interactive Nanometrology Visualizer

Figure 1: 1D lock-in differential capacitance (dC/dV) and extracted active carrier concentration (N_act). Notice the bipolar swing: positive signal on n-type region, negative on p-type region, and the zero-crossing defining the metallurgical junction ($X_j$).

Figure 2: 2D Spatial SCM phase & amplitude lock-in map. Red tones represent n-type carriers (source/drain extensions), blue tones represent p-type substrate/channel, and the dashed line marks the zero-crossing electrical junction boundary under the AFM diamond tip apex.

Figure 3: Tip-sample nanoscale MOS capacitance-voltage ($C\text{–}V$) curve and its derivative ($dC/dV$) showing accumulation, depletion, and the operational lock-in modulation window ($V_{\text{dc}} \pm V_{\text{ac}}$).

20-Year Semiconductor Fab Tool Financial Model (DCF)

Cleanroom SCM AFM module capital expenditure, diamond probe OPEX, yield excursion mitigation, and net present value.

Advanced Metrology ROI
AFM SCM resonator & cleaver
Diamond cantilevers & helium/N2 purge
Excursion prevention & fast root cause
Hurdle rate for fab capital investments
Year Net Annual Benefit Discount Factor Discounted Cash Flow Cumulative Discounted Cash (NPV)

Comprehensive Technical Guide: Scanning Capacitance Microscopy (SCM)

1. Tip-Sample Nanoscale MOS Physics

Scanning Capacitance Microscopy utilizes a conductive atomic force microscope (AFM) cantilever bearing a metal-coated (PtIr) or doped diamond apex scanning across a cross-sectioned semiconductor specimen. An ultra-thin interfacial dielectric oxide layer (0.5 to 2.0 nm native or UV-ozone grown $\text{SiO}_2$) creates a local nanoscale Metal-Oxide-Semiconductor (MOS) structure:

C_total = ( 1 / C_ox + 1 / C_dep )⁻¹

Applying a sinusoidal AC modulation voltage $V_{\text{ac}} \sin(\omega t)$ alternately expands and contracts the local semiconductor depletion region depth $W_d = \sqrt{2 \epsilon_s |V - V_{\text{fb}}| / (q N_{\text{act}})}$, creating a periodic capacitance change that is detected with phase-sensitive lock-in demodulation.

2. Polarity Discrimination & dC/dV Zero-Crossing

The defining advantage of SCM over resistance-based techniques (like SSRM) is its intrinsic sensitivity to carrier polarity:

  • P-Type Semiconductor: Positive tip bias pushes holes away into deeper depletion, decreasing capacitance ($dC/dV < 0$, lock-in phase $\approx 180^\circ$).
  • N-Type Semiconductor: Positive tip bias pulls electrons toward the surface into accumulation, increasing capacitance ($dC/dV > 0$, lock-in phase $\approx 0^\circ$).
  • Metallurgical P-N Junction: At the boundary where net active dopant concentration transitions through zero, $dC/dV = 0$, giving an unambiguous spatial marker for electrical junction depth ($X_j$).

3. Ultra-High Frequency (UHF) Resonant Detection

Because nanoscale tip-sample capacitance changes are extraordinarily minute (often less than $0.1\text{ aF} = 10^{-19}\text{ F}$), traditional audio-frequency bridge circuits are overwhelmed by stray parasitic capacitance. SCM couples the cantilever tip directly into a coaxial or microstrip resonator tuned to $0.9\text{–}1.3\text{ GHz}$. Nanoscale tip capacitance shifts modulate the resonator's center frequency, which is translated into a millivolt output with zeptofarad sensitivity ($10^{-21}\text{ F}/\sqrt{\text{Hz}}$).

4. Dynamic Range & In-Fab Yield Economics

In modern sub-3nm nodes, gate-all-around (GAA) nanosheets and FinFETs require strict lateral abruptness control ($< 2.0\text{ nm/decade}$) to prevent punch-through leakage. While SIMS yields 1D chemical dopant profiles averaged over wide areas, SCM provides true 2D cross-sectional active carrier mapping directly on production test structures within hours, eliminating multimillion-dollar line yield excursions before entire wafer lots complete back-end processing.

Formative Assessment: SCM & dC/dV Metrology Quiz

3 Questions

1. How does SCM determine the exact physical location of a metallurgical p-n junction?

2. Why does a lightly doped semiconductor region produce a larger SCM lock-in dC/dV signal than a heavily doped region?

3. What lock-in signal characteristic distinguishes n-type carriers from p-type carriers in SCM?

Frequently Asked Questions

SCM operates by forming a nanoscale Metal-Oxide-Semiconductor (MOS) capacitor between a conductive AFM tip, a thin native or thermal oxide dielectric, and the semiconductor sample. When a small AC bias Vac is applied, the lock-in amplifier detects the differential capacitance derivative dC/dV. Because positive tip voltage induces depletion in p-type semiconductors (reducing capacitance, dC/dV < 0, 180° phase) but induces accumulation in n-type semiconductors (increasing capacitance, dC/dV > 0, 0° phase), the lock-in phase directly reveals carrier polarity. At the metallurgical junction where net active doping is zero, dC/dV crosses zero.

In a depleted MOS capacitor, the depletion layer depth Wd scales inversely with the square root of dopant concentration: Wd = sqrt(2 * eps_s * |V - Vfb| / (q * N)). In lightly doped regions, the depletion width expands substantially with applied AC voltage, causing a large modulation in depletion capacitance (high dC/dV). In heavily doped regions (such as source/drain contacts), the depletion region is pinned extremely thin, producing minimal capacitance modulation (low dC/dV). Thus, |dC/dV| roughly scales as N^(-1/2).

While Scanning Spreading Resistance Microscopy (SSRM) measures local contact resistance under heavy tip pressure to obtain active carrier concentrations across 7 decades with sub-nanometer spatial resolution, SSRM does not intrinsically reveal carrier polarity without complex polarity switching. SCM, in contrast, directly provides bipolar polarity information (+dC/dV for n-type vs -dC/dV for p-type), locating the electrical metallurgical p-n junction precisely at the dC/dV = 0 zero-crossing.

The nanoscale tip-sample capacitance is exceedingly small, typically on the order of 0.1 to 10 attofarads (10^-18 F). Standard low-frequency capacitance bridges cannot detect changes this tiny above stray cable capacitances. SCM connects the tip directly to a high-Q UHF transmission line resonator (operating at 0.9 to 1.3 GHz). Tiny variations in tip capacitance shift the resonator frequency (delta_f = -f0 * delta_C / (2 * C0)), which is detected as an amplitude or frequency modulation with sub-attofarad (zeptofarad) sensitivity.

An advanced cleanroom SCM AFM module represents a capital expenditure of $680,000 to $850,000 with annual operating costs of $65,000. By enabling in-fab 2D dopant delineation within 4 hours (compared to 5-day turnaround for external SIMS or TEM sample preparation), fab engineering teams prevent wafer scrap excursions, tune source/drain halo implants, and accelerate sub-3nm node yield ramps, generating $1.8M to $2.4M in annual value. This delivers a discounted payback period of 1.5 to 1.8 years and a 20-year net present value exceeding $17M at an 8% hurdle rate.

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