Sub-1nm CMOS • 3D Monolithic Stacking • Angstrom Era

Complementary FET (CFET) & 3D Lab

Simulate 3D Complementary FET (CFET) monolithic nMOS/pMOS vertical stacking, vertical N2P dielectric isolation, 3T standard cell scaling, and a 20-year foundry fab DCF model.

Target Generation: A10 / A7 Angstrom Nodes (<1nm) • Architecture: Monolithic 3D Stacked GAA • Cell Density: 3.0T to 3.5T Tracks (-45% Footprint)

Standard Cell Shrink

-45.0% Area

Zero Lateral N2P Deadspace

Effective Channel Width

122 nm Weff

2 sheets / device tier

Drive Current (Ion)

153 μA / tier

Ballistic carrier injection

Contact Trench Aspect Ratio

4.8:1 (91 nm)

Dual-tier MOL contact etch

Intrinsic Inverter Delay

0.80 ps

High transconductance / Cgd

Self-Heating Penalty

+23.1 °C ΔT

Upper tier thermal budget

Vertical N2P Gap

18 nm Dielectric

Zero lateral boundary space

20-Yr Foundry NPV

$184.20M

WACC 9.5% discounted cash

Capital Payback

Year 3

Module CapEx $28.0M

CFET Architecture & Device Controls

CFET Integration Architecture

Choose between monolithic single-wafer superlattice and sequential wafer-bonded tiers.

Nanosheet Ribbon Channel Width (nm) 25 nm

12 nm (Narrow Wire) 25 nm (Standard Ribbon) 45 nm (High-Drive Sheet)

Nanosheet Channel Thickness (nm) 5.5 nm

4.0 nm (Quantum Confinement) 5.5 nm 10.0 nm (Thick Channel)

Vertical N2P Dielectric Isolation Gap (nm) 18 nm

10 nm (Aggressive Scaling) 18 nm 40 nm (Robust Isolation)

Nanosheets per Transistor Tier (nMOS / pMOS) 2 sheets/tier

1 (Single Sheet) 2 (Dual Sheet Standard) 3 (Triple Sheet Server)

Standard Cell Track Height (Tracks) 3.5T

3.0T (Aggressive Angstrom) 3.5T (Standard CFET) 5.5T (Relaxed Hybrid)

CFET Foundry Business & Module Economics

Annual 300mm CFET Wafers Fabricated 25k wafers

Advanced CFET Wafer ASP ($ / Wafer) $9800

Multiphysics CFET & Standard Cell Panels

Real-Time Reactive Model

Models monolithic 3D nMOS/pMOS stacking, standard cell 6T vs 3.5T footprint reduction, dual-tier gate workfunction tuning, and 20-year foundry cash flows.

Logic Density: >40% Area Reduction

N2P Overhead: 0 nm Lateral Space

Node Target: Sub-1nm (A10 / A7)

20-Year CFET Semiconductor Foundry DCF Financial Projections

Models cleanroom equipment CapEx ($28.0M), high-selectivity SiGe ALD/ALE tool depreciation, cleanroom labor COGS, and free cash flows.

10-Year Straight-Line Depreciation

Year	Revenue ($M)	COGS ($M)	OpEx ($M)	Free Cash Flow ($M)	Cumulative Cash ($M)

Engineering Principles: Complementary Field-Effect Transistors

In leading-edge digital electronics, standard cell library scaling has exhausted the geometric benefits of conventional planar and lateral FinFET architectures. Complementary Field-Effect Transistors (CFET) break through this ceiling by vertically stacking complementary n-type and p-type channels in three dimensions, defining the standard for Angstrom-era nodes ($A10$, $A7$).

1. Vertical Stacking & Zero Lateral N2P Space

In lateral Gate-All-Around nanosheets, physical isolation requires a lateral boundary space between nMOS and pMOS fins ($N2P \approx 30 - 45\text{ nm}$). This inactive buffer region consumes up to $35\%$ of total standard cell area.

CFET places the nMOS nanosheets directly above the pMOS nanosheets (or vice versa), separated by a thin dielectric inner spacer layer ($15 - 20\text{ nm}$). This reduces cell width by approximately $50\%$, allowing standard logic cells to shrink from $6.0\text{T}$ down to $3.0\text{T}$ or $3.5\text{T}$ track heights.

2. Monolithic Superlattice vs. Sequential Layer Transfer

Two primary fabrication methodologies enable CFET architectures:

Monolithic 3D CFET: Alternating $\text{Si}$ and $\text{Si}_{1-x}\text{Ge}_x$ layers are epitaxially grown on a single crystalline silicon wafer in a single superlattice run. Complex chemical dry etching selectively hollows out the $\text{SiGe}$ sacrificial layers, leaving suspended silicon nanosheets in two distinct vertical tiers.
Sequential 3D CFET: The bottom transistor tier is processed up to the contact level, followed by direct dielectric fusion bonding ($\text{SiO}_2$ or $\text{Al}_2\text{O}_3$) of a top active layer. This permits distinct channel materials (e.g. high-mobility germanium pFET on silicon nFET) but requires precise sub-10nm tier-to-tier alignment.

3. Dual Workfunction Gate ALD & Self-Heating

Because nFET and pFET operate in the same vertical column, threshold voltage tuning requires deposition of dual workfunction metals (n-WFM like $\text{TiAlC}$ and p-WFM like $\text{TiN}$) inside sub-20nm cavities. Furthermore, the upper tier is thermally isolated from the substrate by lower dielectric layers, increasing upper-tier channel operating temperatures by $15 - 25^\circ\text{C}$ due to self-heating.

Knowledge Check: CFET Architecture Mastery

1. What is the primary physical reason CFET enables a 40 to 50 percent cell area shrink?

It eliminates the gate dielectric layer entirely.

It stacks nMOS directly on top of pMOS vertically, eliminating lateral n-to-p (N2P) boundary space from the cell footprint.

It replaces all copper wires with carbon nanotubes.

2. How does Monolithic CFET create stacked nanosheets on a single silicon wafer?

By epitaxially growing an alternating superlattice of Si and SiGe layers, followed by selective etching of the SiGe sacrificial layers.

By folding a thin silicon ribbon physically using robotic tweezers.

By printing transistors sequentially using an ink-jet printer.

3. Why does the top transistor tier in a CFET suffer higher self-heating than the bottom tier?

It is exposed to ambient cleanroom lighting.

The top tier carries zero electrical current.

The top tier is thermally isolated from the bulk silicon substrate by multiple low-conductivity dielectric and gate layers.

Frequently Asked Questions About Complementary Field-Effect Transistors and 3D Logic

In standard Gate-All-Around (GAA) nanosheet architectures, nMOS and pMOS transistors reside side-by-side on the wafer surface, requiring dead-space lateral isolation known as n-to-p (N2P) boundary space. Complementary FET (CFET) folds the standard CMOS inverter into three dimensions by stacking an nMOS nanosheet transistor directly on top of a pMOS transistor (or vice versa). This vertical integration eliminates lateral N2P boundary overhead entirely, reducing standard logic cell footprint area by 40 to 50 percent.

Monolithic CFET grows both bottom and top transistor channels on a single substrate using continuous epitaxy of alternating silicon and silicon-germanium superlattice layers, followed by complex selective etching to release both nanosheet tiers. Sequential CFET fabricates the bottom transistor tier first, bonds a top active tier via low-temperature wafer-to-wafer direct dielectric bonding, and finishes the top tier. Sequential CFET allows different channel materials like germanium or III-V on silicon but requires sub-10nm layer transfer alignment.

Standard cell track height indicates the number of routing tracks available for metal interconnects. Conventional FinFETs and nanosheets require 5 to 6 tracks to accommodate lateral nMOS and pMOS channels alongside frontside power rails. By stacking nMOS and pMOS vertically and combining CFET with Backside Power Delivery Networks (BSPDN), the cell width can be halved and the track height compressed to 3.0 or 3.5 tracks, enabling the true continuation of scaling below 1 nanometer.

The primary challenges include high-aspect-ratio middle-of-line contact etching (aspect ratios exceeding 14:1) that must contact bottom source/drain terminals without shorting top terminals, dual workfunction metal gate patterning in an extremely narrow vertical cavity, and self-heating in the upper tier. Because the top transistor is isolated from the bulk silicon substrate by dielectric inner spacers, heat dissipation is restricted, increasing peak junction temperatures by 10 to 25 degrees Celsius.

Equipping a commercial 300mm CFET manufacturing cleanroom module requires approximately $28.0 million in initial CapEx. Core investments comprise multi-chamber selective isotropic atomic layer etching tools for sacrificial SiGe nanosheet release ($8.2M), dual-workfunction atomic layer deposition systems for independent n/p threshold tuning ($6.9M), high-aspect-ratio reactive ion etching and low-damage middle-of-line metallization cells ($7.1M), and advanced optical scatterometry with in-situ TEM verification suites ($5.8M).

Related Nanoscale Semiconductor & 3D Logic Laboratories

X-Ray Metrology

CD-SAXS Metrology Lab

3D nanosheet profiling, high-aspect-ratio holes & tool foundry DCF.

Sub-2nm Logic

Backside Power Delivery (BSPDN)

Nano-TSV contacts, IR drop elimination & 20-yr foundry DCF.

3D Packaging

Direct Cu-Cu Hybrid Bonding

Sub-micron pad pitch, CMP dishing kinetics & packaging foundry DCF.

Cryogenic ASIC

Cryo-CMOS Quantum Lab

4K subthreshold steepening, qubit control & foundry DCF.