3D Packaging & Thermal FA Lab

Lock-In Thermography (LIT) Lab

Model thermal diffusion waves, phase-shift vertical depth deconvolution in 3D stacked ICs, sub-millikelvin hot spot localization, and 20-year semiconductor FA tool DCF.

Micro-short inside Through-Silicon Via (TSV) on layer 7 of a 12-high HBM3 memory stack. Phase lag deconvolution pinpoints exact vertical die layer non-destructively.

Lock-In Modulation & Material Controls

250 µW
20 µW (Faint leakage) 5.0 mW (Hard short)
10.0 Hz
0.5 Hz (Deep penetration) 100 Hz (Sharp spatial res)
320 µm
2 µm (Surface) 600 µm (Deep 3D stack)
24.0 µm
5.0 µm 55.0 µm
300 s
10 s (Fast scan) 900 s (Ultra-low noise)
1.10 V
0.5 V (Core logic) 20.0 V (Power SiC)

Thermal Wave FA Visualizer

Figure 1: 2D Lock-In Thermography (LIT) amplitude heatmap. The bright circular hotspot indicates the surface thermal wave emergence point above the buried defect, pinpointed by the reticle crosshair.

Figure 2: Lock-in phase shift (Δφ) vs. square root of frequency (√f). The linear slope $d(\Delta\phi)/d(\sqrt{f}) = -z\sqrt{\pi/D_{\text{th}}}$ directly deconvolves the buried defect depth $z$.

Figure 3: Cross-sectional view of 3D stacked dies (e.g. 12-high HBM memory stack). The thermal wave propagates upward toward the infrared camera, allowing non-destructive layer isolation.

20-Year Advanced Packaging FA Tool Financial Model (DCF)

Cooled MWIR camera system CapEx, cryocooler maintenance, CoWoS/HBM package scrap avoidance, and net present value.

Advanced Packaging ROI
InSb cooled camera + lock-in engine
Cryocooler service & calibration
CoWoS/HBM non-destructive triage
Semiconductor fab hurdle rate
Year Net Annual Benefit Discount Factor Discounted Cash Flow Cumulative Discounted Cash (NPV)

Comprehensive Technical Guide: Lock-In Thermography (LIT)

1. Thermal Diffusion Wave Physics

When an electrical failure site (such as an ohmic short, reverse-bias junction leakage, or gate oxide pinhole) is energized periodically at frequency $f_{\text{lockin}}$, heat is generated as an oscillating point source. Because thermal propagation is diffusive rather than wave-like in the conventional sense, it behaves as a heavily damped “thermal diffusion wave” with characteristic decay length $\mu_{\text{th}}$:

μ_th = √( D_th / (π × f_lockin) )

In silicon ($D_{\text{th}} \approx 8.9 \times 10^{-5}\text{ m}^2/\text{s}$), $\mu_{\text{th}} \approx 530\,\mu\text{m}$ at $10\text{ Hz}$, but shrinks to $\approx 168\,\mu\text{m}$ at $100\text{ Hz}$, enabling frequency-tuned trade-offs between depth penetration and lateral spatial confinement.

2. Non-Destructive 3D Depth Deconvolution

In heterogeneous 2.5D/3D architectures (such as TSMC CoWoS, Intel Foveros, and 12-high HBM3 memory stacks), physical cross-sectioning destroys adjacent good silicon. LIT extracts the thermal phase lag $\Delta \phi$ between the electrical excitation trigger and the surface infrared temperature response:

Δφ = -z / μ_th = -z × √( π × f / D_th )

Plotting $\Delta \phi$ across multiple frequencies reveals a linear slope with $\sqrt{f}$, directly resolving the buried vertical coordinate $z$ to pinpoint the exact defective die layer without opening the package.

3. Sub-Millikelvin Noise Suppression

Standard infrared cameras have an instantaneous thermal sensitivity (NETD) of approximately $15\text{–}25\text{ mK}$, which is inadequate for faint leakage currents dissipating under $100\,\mu\text{W}$. By integrating the synchronized lock-in signal over $10^4\text{ to }10^5$ frames ($3\text{–}10\text{ minutes}$), random noise decreases as $1/\sqrt{N_{\text{frames}}}$, achieving noise floors below $10\,\mu\text{K}$ ($0.01\text{ mK}$) and detecting power dissipation down to the microwatt regime.

4. Advanced Packaging Economics

High-performance AI processors combine a massive host compute die with multiple HBM stacks on a large silicon interposer. If an assembled module fails electrical testing, scrap costs exceed $\$1,500\text{ to }\$4,000$ per package. In-house LIT delivers fast, non-destructive root-cause localization within 2 hours, identifying whether the failure resides in the substrate, interposer microbump, or a specific memory die, driving multi-million-dollar annual savings.

Formative Assessment: Lock-In Thermography Quiz

3 Questions

1. How does LIT determine the vertical depth of a defect in a 3D stacked integrated circuit?

2. What is the effect of increasing the lock-in modulation frequency f_lockin?

3. Why can LIT detect microwatt-level hot spots with temperature rises below 100 microkelvin?

Frequently Asked Questions

LIT applies a periodic square-wave electrical excitation to the integrated circuit at frequency f_lockin, causing defect sites to dissipate power periodically. An infrared camera captures consecutive thermal frames synchronized with the modulation. Through Fourier lock-in demodulation over thousands of frames, ambient thermal drift and uncorrelated sensor noise are filtered out. The effective noise floor drops from ~20 mK down to below 10 microkelvin (< 0.01 mK), enabling the detection of microwatt power dissipation.

When a buried heat source oscillates periodically, it generates a damped thermal diffusion wave propagating toward the surface. The phase lag Delta_phi of the wave increases linearly with depth z: Delta_phi = -z / mu_th = -z * sqrt(pi * f / D_th), where mu_th is the thermal diffusion length. By measuring the phase lag across multiple lock-in frequencies, failure analysts can isolate the precise vertical die layer in an HBM 3D stack (e.g. Die #7 vs Die #8) without destructive cross-sectioning.

The thermal diffusion length mu_th scales inversely with the square root of frequency: mu_th = sqrt(D_th / (pi * f)). At low frequencies (e.g., 1 Hz), thermal waves propagate millimeters, enabling deep penetration but producing wide, blurred thermal halos. At higher frequencies (e.g., 50 to 100 Hz), the thermal wave is tightly confined within tens of microns, dramatically sharpening lateral spatial resolution to pinpoint sub-micron defect coordinates.

OBIRCH uses an external focused infrared laser to scan the circuit and measure resistance changes (passive thermal stimulation), whereas LIT modulates the internal electrical power of the device itself and measures emitted infrared radiation (active thermal emission). LIT is non-contact, covers whole packages or 300mm wafers in a single field of view, and excels at vertical 3D depth localization in advanced packaging (CoWoS, HBM, 3D ICs).

An advanced cooled MWIR lock-in thermography suite requires a capital expenditure of $650,000 to $950,000 with annual maintenance of $55,000. By enabling non-destructive 3D packaging defect isolation within hours rather than 2 weeks of high-risk mechanical polishing, the tool prevents scrap of expensive multi-chip modules ($1,500+ per unit) and accelerates yield learning, delivering $1.9M to $2.8M in annual benefits. This results in an IRR of 54% to 68% and a discounted payback period of 1.4 to 1.7 years.

Related Failure Analysis & Metrology Simulations

OBIRCH Fault Isolation Lab

Model through-silicon infrared laser stimulation, thermal resistance changes (OBIRCH/TIVA), and FA DCF.

SCM Carrier Profiling Lab

Model tip-sample nano-MOS differential capacitance (dC/dV), 2D carrier polarity delineation, and fab tool DCF.

SSRM Carrier Profiling Lab

Model spreading resistance, gigapascal contact pressure phase transitions, active dopants, and fab tool DCF.

EBIC Semiconductor Lab

Model electron-beam induced current, minority diffusion lengths, junction collection, and defect contrast.

Cathodoluminescence Lab

Model electron-beam excitation, sub-50nm hyperspectral emission, and dislocation dark spots.

DLTS Defect Spectroscopy Lab

Model deep-level trap emission kinetics, rate-window boxcar deconvolution, and power fab DCF.