What role does the 1,600 C CVD homoepitaxial drift layer play on a 4H-SiC wafer?

Bulk PVT-grown 4H-SiC substrates are heavily nitrogen-doped (n+) for mechanical support and low backside resistance, but contain too many defects and carriers to block 1,200 V to 3,300 V directly. After Chemical-Mechanical Planarization (CMP), wafers enter a 1,600 degrees C hot-wall CVD reactor where silane (SiH4) and propane (C3H8) in H2 carrier gas deposit a 10-30 micrometer ultra-pure, precisely nitrogen-doped 4H-SiC homoepitaxial drift layer with basal plane dislocation (BPD) conversion >99%.

Why are 800V EV automakers transitioning traction inverters from Silicon IGBTs to 4H-SiC MOSFETs?

Compared to silicon (E_g = 1.12 eV), 4H-SiC has a 3.26 eV wide bandgap, a 10x higher critical breakdown electric field (2.8 MV/cm), and 3x higher thermal conductivity (4.9 W/cm-K). By Baliga's Figure of Merit (proportional to E_c^3), a 1,200 V 4H-SiC MOSFET uses a 10x thinner drift layer with 100x lower specific on-resistance and eliminates IGBT tail-current switching losses, extending EV driving range by 5-8% or reducing battery pack cost by $600-$1,000 per vehicle.

Silicon Carbide (SiC) PVT Growth & 200mm Wafer Lab

Q: Why must 4H-SiC boules be grown by 2,300 C Physical Vapor Transport (PVT) instead of Czochralski melt pulling?

Unlike elemental silicon (which melts congruently at 1,414 degrees C), silicon carbide has no stoichiometric liquid phase at practical pressures; above ~2,700 degrees C it decomposes peritectically into liquid silicon and solid graphite. Consequently, 4H-SiC boules are grown via the Modified Lely / Physical Vapor Transport (PVT) method: 6N SiC source powder is heated to 2,200-2,400 degrees C at 5-30 mbar Ar/N2 inside an induction-heated isostatic graphite crucible, subliming into Si(g), Si2C(g), and SiC2(g) vapors that condense onto a slightly cooler 4H-SiC seed crystal at 0.25-0.45 mm/hr.

Q: How is 6N (99.9999%) semiconductor-grade SiC source powder synthesized and purified?

High-purity quartz sand (SiO2) and low-ash carbon react carbothermically at 2,200-2,500 degrees C (SiO2 + 3C -> SiC + 2CO, delta H = +618.5 kJ/mol), or ultra-pure silanes and hydrocarbons react directly in CVD/self-propagating synthesis reactors. To remove electrically active boron (B), aluminum (Al), titanium (Ti), and vanadium (V) down to <0.1 ppmw (6N purity), the SiC granules undergo high-temperature halogenation (Cl2/HCl gas at 1,800-2,000 degrees C), which volatilizes trace metals as gaseous chlorides (BCl3, AlCl3, FeCl3, TiCl4).

Q: Why does sub-surface laser wafer splitting dramatically improve 200mm 4H-SiC fab economics over diamond wire sawing?

Because silicon carbide has a Mohs hardness of 9.2-9.5 (second only to diamond) and PVT crystal growth takes 6-8 days to grow a 40-45 mm puck, conventional diamond multi-wire sawing (~0.72-0.80 mm pitch) grinds nearly 40% of the crystal into lost kerf slurry while taking 40-60 hours per boule. Sub-surface laser splitting focuses a pulsed laser inside the crystal to create a cleavage plane (~0.50-0.55 mm effective pitch), boosting prime wafer output per boule by 30-40%.

Industrial PVT Crystal Growth & 200mm 4H-SiC Megafab Presets

Load calibrated PVT sublimation furnace, laser wafering, and HVDC thick-epi benchmarks:

Prime 4H-SiC Epi-Wafers

327,264 wafers/yr

40.1 prime wafers/boule (8,160 boules)

800V EV Capacity Enabled

5.07M EVs/yr

800V 1,200V SiC MOSFET Inverters

6N Powder & Tech SiC

34.3 t/yr 6N SiC

+ 12,000 t/yr Acheson α-SiC

Annual EBITDA

$235.12M

55.3% EBITDA Margin | Rev: $425.10M

20-Year Project NPV

$1,182.40M

IRR: 29.8% | Payback: 3.4 yrs

Net Cost / Prime Wafer

$431/wafer

Total Fab Power: 158.5 GWh/yr

1. PVT Sublimation Furnaces, Boule Kinetics & Wafering Pitch

Active 2,300°C PVT Crystal Growth Furnaces 240 furnaces

PVT Growth Rate 0.32 mm/hr

Growth Hours / Run 140 hrs

Furnace Runs / Yr 34 runs/yr

Slicing Pitch (Wafer+Kerf) 0.72 mm/wafer

Crystal & Epi Yield (%) 76.0%

Acheson α-SiC (t/yr) 12,000 t/yr

2. Wafer ASP, Graphite Crucibles, CMP/Epi Cost & Fab CAPEX

Prime 4H-SiC Wafer ASP $1,150/wafer

Technical α-SiC ($/t) $1,850/t

Crucible & 6N Charge $4,200/run

Slicing, CMP & CVD Epi $210/wafer

Power ($/MWh) $68/MWh

CAPEX ($M) $580M

WACC (%) 8.5%

Interactive 6N SiC Synthesis, 2,300°C PVT Boule Growth & 200mm Epi-Wafer Flowsheet

4H-SiC E_g = 3.26 eV | E_c = 2.8 MV/cm

Silicon Carbide PVT Crystal Growth, Wafering and Energy Balance
Process Parameter	Output / Metric
Annual PVT Crystal Runs	8,160 boules/yr (240 furnaces × 34)
4H-SiC Boule Thickness	44.8 mm gross / 38.0 mm net
Wafer Yield per Boule	52.8 sliced → 40.1 prime wafers/boule
Prime 4H-SiC Epi-Wafers	327,264 prime 4H-SiC epi-wafers/yr
Test / Mechanical Wafers	46,506 test/dummy SiC wafers/yr
6N SiC Source Powder	34.3 t/yr 6N SiC source powder
Co-Product Technical α-SiC	12,000 t/yr metallurgical/ceramic α-SiC
Total Fab & Kiln Electricity	158,521 MWh/yr (76,704 MWh PVT/Epi)
800V EV Inverters Enabled	5.07 Million 800V EV traction inverters/yr

Annual Revenue and Operating Cost Breakdown
Revenue / Cost Line	Annual ($M/yr)
Prime 200mm 4H-SiC Epi-Wafers	$376.35M
Co-Product Technical Acheson α-SiC	$22.20M
Test / Dummy Mechanical Wafers	$11.77M
Total Gross Revenue	$410.32M
Isostatic Graphite Crucibles & 6N Charge	$34.27M
Wafering, Nanodiamond CMP & CVD Epi	$68.73M
Quartz Sand & Low-Ash Carbon Feed	$7.21M
PVT Induction & Acheson Electricity	$10.78M
Cleanroom Metrology, Labor & Fixed O&M	$45.90M
Total Operating Cost (OPEX)	$166.89M
Annual EBITDA (Margin)	$243.43M (59.3%)

20-Year Project NPV & IRR Sensitivity Matrix: Crystal/Epi Yield vs. Prime 4H-SiC Wafer ASP

20-Year Discounted Cash Flow (DCF) Pro-Forma Schedule

10-Year Straight-Line Depreciation | 21% Corporate Tax | 1.2%/yr Escalation

20-Year financial cash flow projection for 200mm 4H-SiC PVT crystal growth and epi-wafer manufacturing
Year	Prime Wafers	EVs Enabled	Revenue ($M)	OPEX ($M)	EBITDA ($M)	Taxes ($M)	Free Cash Flow ($M)	Discounted FCF ($M)	Cumulative FCF ($M)

Governing Carbothermic, PVT Sublimation & Wide-Bandgap Physics Equations

1. Acheson Carbothermic Synthesis

High-purity quartz sand and low-ash carbon react above 2,200°C to synthesize crystalline silicon carbide:

{SiO}_{2} + 3 C \to α -SiC + 2 CO ↑

Strongly endothermic (ΔH°₂₉₈ = +618.5 kJ/mol); requires 1.498 t SiO₂ and 0.899 t C per tonne SiC.

2. PVT Sublimation Vapor Transport

At 2,300°C and 5–30 mbar Ar/N₂, 6N SiC source powder sublimes incongruently into three primary gas species:

3 {SiC}_{(s)} ⇌ {Si}_{(g)} + {Si}_{2} C_{(g)} + {SiC}_{2 (g)} + C_{(s)}

Driven by a 15–30°C/cm axial thermal gradient, vapor species crystallize as single-polytype 4H-SiC at 0.25–0.45 mm/hr.

3. Baliga's Figure of Merit (BFOM)

Unipolar power MOSFET drift-region conduction loss scales inversely with the cube of critical breakdown field (E_c):

R_{on,sp} = \frac{4 V_{BV}^{2}}{ε_{s} μ_{n} E_{c}^{3}}

Because E_c(4H-SiC) ≈ 2.8 MV/cm (~10× Si), specific on-resistance R_on,sp is >500× lower than silicon at 1,200 V.

4H-SiC PVT Crystal Growth, Wafering & EV Power Electronics Mastery Quiz

Frequently Asked Questions (FAQ)

Unlike elemental silicon (which melts congruently at 1,414°C), silicon carbide has no stoichiometric liquid phase at practical pressures; above ~2,700°C it decomposes peritectically into liquid silicon and solid graphite. Consequently, 4H-SiC boules are grown via the Modified Lely / Physical Vapor Transport (PVT) method: 6N SiC source powder is heated to 2,200–2,400°C at 5–30 mbar Ar/N₂ inside an induction-heated isostatic graphite crucible, subliming into Si_(g), Si₂C_(g), and SiC_2(g) vapors that condense onto a slightly cooler 4H-SiC seed crystal at 0.25–0.45 mm/hr.

High-purity quartz sand (SiO₂) and low-ash carbon react carbothermically at 2,200–2,500°C (SiO₂ + 3C → SiC + 2CO, ΔH = +618.5 kJ/mol), or ultra-pure silanes and hydrocarbons react directly in CVD/self-propagating synthesis reactors. To remove electrically active boron (B), aluminum (Al), titanium (Ti), and vanadium (V) down to <0.1 ppmw (6N purity), the SiC granules undergo high-temperature halogenation (Cl₂/HCl gas at 1,800–2,000°C), which volatilizes trace metals as gaseous chlorides (BCl₃, AlCl₃, FeCl₃, TiCl₄).

Because silicon carbide has a Mohs hardness of 9.2–9.5 (second only to diamond) and PVT crystal growth takes 6–8 days to grow a 40–45 mm puck, conventional diamond multi-wire sawing (~0.72–0.80 mm pitch) grinds nearly 40% of the crystal into lost kerf slurry while taking 40–60 hours per boule. Sub-surface laser splitting focuses a pulsed laser inside the crystal to create a cleavage plane (~0.50–0.55 mm effective pitch), boosting prime wafer output per boule by 30–40%.

Bulk PVT-grown 4H-SiC substrates are heavily nitrogen-doped (n⁺) for mechanical support and low backside resistance, but contain too many defects and carriers to block 1,200 V to 3,300 V directly. After Chemical-Mechanical Planarization (CMP), wafers enter a 1,600°C hot-wall CVD reactor where silane (SiH₄) and propane (C₃H₈) in H₂ carrier gas deposit a 10–30 µm ultra-pure, precisely nitrogen-doped 4H-SiC homoepitaxial drift layer with basal plane dislocation (BPD) conversion >99%.

Compared to silicon (E_g = 1.12 eV), 4H-SiC has a 3.26 eV wide bandgap, a 10× higher critical breakdown electric field (2.8 MV/cm), and 3× higher thermal conductivity (4.9 W/cm·K). By Baliga's Figure of Merit (proportional to E_c³), a 1,200 V 4H-SiC MOSFET uses a 10× thinner drift layer with 100× lower specific on-resistance and eliminates IGBT tail-current switching losses, extending EV driving range by 5–8% or reducing battery pack cost by $600–$1,000 per vehicle.