Silicon Photonics Foundry Presets
Load calibrated 300mm SOI foundry, AI CPO megafab, and 800G transceiver benchmarks:
Wafer Starts, Die Footprint, Packaging & Costs
Silicon Photonics & CPO Packaging Process Flowsheet
| Process Parameter | Output / Metric |
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| Revenue / Cost Line | Annual ($M/yr) |
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20-Year NPV & IRR Sensitivity: CMOS Fab Yield vs. PIC Engine ASP
20-Year Discounted Cash Flow (DCF) Pro-Forma Schedule
10-Year Straight-Line Depreciation | 21% Tax | 1.5%/yr ASP Erosion| Year | Engines (M) | Bandwidth | Revenue ($M) | OPEX ($M) | EBITDA ($M) | Taxes ($M) | Free Cash Flow ($M) | Discounted FCF ($M) | Cumulative FCF ($M) |
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Governing Integrated Photonics & Modulator Physics Relations
1. Optical Confinement
High index contrast waveguide mode condition:
Δn = nSi (3.48) − nSiO₂ (1.44) ≈ 2.04
Allows sub-micron 450×220 nm single-mode waveguide cores with bend radii <5 µm.
2. Plasma Dispersion Effect
Free-carrier absorption and phase modulation:
Δn = −[8.8×10−22 ΔNe + 8.5×10−18 (ΔNh)0.8]
Modulates effective index in Mach-Zehnder arms achieving VπL ∼ 1.5–2.2 V·cm.
3. Germanium Responsivity
Photocurrent generated per incident optical watt:
R = (q × ηqe × λ) / (h × c)
At 1310 nm with quantum efficiency >85%, responsivity reaches 0.9–1.0 A/W.
Silicon Photonics & CPO Foundry Mastery Quiz
Frequently Asked Questions (FAQ)
Silicon is transparent at 1310 nm and 1550 nm telecom wavelengths. The high refractive index contrast between the silicon waveguide core (n ≈ 3.48) and the silicon dioxide cladding (n ≈ 1.44) permits sub-micron optical modes with tight bend radii (<5 µm). Furthermore, fabricating on 300mm SOI leverages billions of dollars in established CMOS lithography, etching, and chemical mechanical polishing tools.
Silicon has an indirect bandgap of 1.12 eV, meaning electron-hole radiative recombination requires momentum assistance from lattice phonons. This results in negligible light emission. Silicon photonics circuits therefore couple external or hybrid-bonded Indium Phosphide (InP) continuous-wave (CW) laser sources into the silicon waveguides.
Traditional pluggable transceivers require long high-frequency copper traces on circuit boards from the switch ASIC to the front panel, consuming significant electrical power in DSP retimers. CPO places the optical engine directly on the multi-chip substrate next to the switch ASIC, reducing electrical trace length from 300 mm to under 50 mm and cutting SerDes energy consumption by 30 to 40 percent.
Because pure silicon is transparent to infrared communications wavelengths, epitaxial Germanium (Ge-on-Si) is selectively grown in etched waveguide cavities. Germanium's smaller direct bandgap allows strong absorption across both the 1310 nm O-band and 1550 nm C-band, achieving responsivity of 0.9 to 1.0 A/W and bandwidths exceeding 50 to 70 GHz.
The model calculates annual 300mm wafer starts, good photonic die counts from die area and CMOS fab yields, and optical engine packaging yields. It accounts for 300mm SOI substrates, lithography and etch processing, external InP laser modules, and fiber array packaging, then generates a 20-year DCF schedule with 1.5 percent annual price erosion and 10-year depreciation.