III-V Compound Semiconductors VCSEL & 5G RF Foundry 20-Year DCF Model

Gallium Arsenide (GaAs) Wafer & VCSEL Optoelectronics Lab

Simulate commercial fabrication economics for 6-inch and 8-inch Gallium Arsenide (GaAs) epi-ready substrates. Model Vertical Gradient Freeze (VGF) crystal growth, liquid boric oxide (B₂O₃) volatile arsenic suppression, low-defect CMP polishing, and 20-year DCF capital budgeting for 850nm AI datacenter VCSELs and 5G smartphone RF front-end modules.

High Electron Mobility ($\mu_e \approx 8,500\text{ cm}^2/\text{V}\cdot\text{s}$) Direct Bandgap ($E_g = 1.424\text{ eV}$) Ultra-Low Dislocation Density (EPD < 1,000 cm⁻²) 100% Client-Side Physics
Target Metric: 850nm AI VCSEL
>140,000
VCSEL Laser Dies per 6-Inch Wafer

<1,000 cm⁻²
VGF Dislocation (EPD)
>10⁷ Ω·cm
SI RF Substrate Resistivity
Manufacturing Presets:
Annual Revenue
$0.00M
Net sales at full capacity
Annual EBITDA
$0.00M (0.0%)
Operating cash margin
Project NPV (8%) / IRR
$0.00M 0.0%
Payback: 0 Years
Dislocation Density (EPD)
<850 cm⁻²
Low-thermal-gradient VGF quality
Integrated Gallium Arsenide (GaAs) Wafer Manufacturing Flowsheet
Step 1: Raw Charge 6N/7N Gallium (48.2%) 6N/7N Arsenic (51.8%) Molten B₂O₃ liquid seal High-purity pBN crucible Step 2: VGF Growth 1,238°C melting point 2–5 MPa Ar overpressure Low thermal gradient Dislocations <1,000 cm⁻² Step 3: Ingot Cropping X-ray crystal orientation Cylindrical grinding Carbon SI vs Si-doped n+ Orientation flat/notch Step 4: Wire Slicing Diamond multi-wire saw Low-kerf 100 μm wire Edge beveling & round TTV < 2.0 μm control Step 5: CMP Polish Double-sided lapping Colloidal silica slurry NaOCl chemo-mechanical Atomic Ra < 0.2 nm Step 6: Device Fab AlGaAs DBR stacks AlAs wet oxidation 850nm VCSEL dies 5G HBT power amps Stoichiometry: 1:1 atomic ratio Mobility: 8,500 cm²/V·s Bandgap: 1.424 eV Direct
Crystal Growth, Wafering & Techno-Economic Inputs
Real-Time Reactive Calculation
Unit Economics & Raw Material Consumption
Metric Value
Average Selling Price (ASP) $380.00
Total Unit COGS per Good Wafer $142.20
Unit Gross Profit Margin $237.80 (62.6%)
Cumulative Fab Yield (Pull + CMP) 77.4%
High-Purity 6N/7N Gallium Consumption 7.8 metric tons/yr
High-Purity 6N/7N Arsenic Consumption 8.4 metric tons/yr
Annual Net Wafers Produced 92.9k wafers/yr
Total Electricity Consumption 4,200 MWh/yr
Optoelectronic Downstream Impact: AI & 5G
Enormous Die Multiplier: Because VCSEL lasers measure just $250\,\mu\text{m} \times 250\,\mu\text{m}$, each 6-inch GaAs wafer yields over 140,000 laser chips.
Annual 850nm VCSEL Lasers Enabled: 13,467M Dies/yr
Powers 400G SR8, 800G SR8, and 1.6T short-reach optical interconnects inside AI server clusters.
Electron Mobility
8,500 cm²/Vs
6x Silicon
Direct Bandgap
1.424 eV
High Quantum Eff.
Die Yield / Wfr
~145,000
VCSEL Chips
20-Year Discounted Cash Flow (DCF) Capital Budgeting Schedule
22% Tax Rate | 10-Yr Linear Depreciation
Period Capacity Ramp Gross Revenue EBITDA Free Cash Flow Discounted FCF Cumulative FCF

Engineering Deep Dive: Thermodynamics, Crystal Pulling & VCSELs

1. Stoichiometry Control & Boric Oxide (B₂O₃) Liquid Seal

Gallium arsenide is a line compound with a congruent melting temperature of $1,238^\circ\text{C}$. Unlike elemental silicon, arsenic exhibits high equilibrium sublimation vapor pressure at high temperatures:

GaAs(l) ⇌ Ga(l) + 1/2 As₂(g) ⇌ Ga(l) + 1/4 As₄(g)
P_eq(As, 1238°C) ≈ 1.0 atm

To prevent rapid arsenic boiling and non-stoichiometric gallium enrichment, the crystal pulling system utilizes liquid encapsulation. A disk of dehydrated, high-purity boric oxide ($\text{B}_2\text{O}_3$, melting point $\sim 450^\circ\text{C}$) melts first and forms an optically transparent liquid blanket floating over the GaAs melt. A counter-pressure of $2 - 5\text{ MPa}$ of inert gas (argon or nitrogen) keeps the liquid seal compressed, preventing arsenic escape.

2. Vertical Gradient Freeze (VGF) vs Legacy LEC Pulling

Historically, GaAs ingots were grown via Liquid Encapsulated Czochralski (LEC), in which a seed crystal is dipped through the $\text{B}_2\text{O}_3$ layer and pulled upwards while rotating. However, the steep axial and radial thermal gradients of LEC induce severe thermal shear stresses:

σ_thermal = E · α_th · (ΔT_radial + ΔT_axial) / (1 - ν)
EPD(LEC) ≈ 10,000 - 50,000 cm⁻²

Modern high-yield fabs employ Vertical Gradient Freeze (VGF). In VGF, the melt is held in a stationary pyrolytic boron nitride (pBN) crucible inside a multi-zone furnace. Solidification is initiated at the bottom seed and propagated upward by slowly decreasing heater temperatures, eliminating mechanical crucible vibrations and dropping the thermal gradient from $>100^\circ\text{C/cm}$ to $<5^\circ\text{C/cm}$. This suppresses dislocation generation, consistently delivering etch pit density $\text{EPD} < 1,000\text{ cm}^{-2}$.


3. Semi-Insulating (SI) GaAs for 5G RF Power Amplifiers

In 5G smartphones, Wi-Fi 7 routers, and satellite phased-array antennas, high-frequency signals ($1 - 40\text{ GHz}$) require Heterojunction Bipolar Transistors (HBTs) and pseudomorphic HEMTs (pHEMTs) with low parasitic substrate capacitance and low RF signal loss.

Conductive substrates would short out RF circuits. To create Semi-Insulating (SI) GaAs:

  • Carbon acceptors ($C_{As}$) are intentionally introduced during growth to compensate residual shallow silicon donors ($Si_{Ga}$).
  • Native deep-level point defects, designated EL2 (an arsenic antisite defect $As_{Ga}$ located at mid-gap, $E_c - 0.75\text{ eV}$), pin the Fermi level precisely at the center of the $1.424\text{ eV}$ bandgap.
  • This pins the intrinsic free carrier concentration to negligible levels, yielding bulk room-temperature electrical resistivity $\rho > 10^7 - 10^8\,\Omega\cdot\text{cm}$.
4. Vertical-Cavity Surface-Emitting Laser (VCSEL) Epitaxy

VCSELs are the dominant optical emitter for short-reach data communications (up to $100\text{ meters}$) in AI clusters (400G/800G SR8 transceivers over OM3/OM4 multimode fiber) and 3D facial LiDAR sensors.

GaAs is uniquely suited for VCSELs because of the near-perfect lattice matching between $\text{GaAs}$ and $\text{AlAs}$ (mismatch $<0.15\%$):

  1. Distributed Bragg Reflectors (DBR): Alternating quarter-wave ($\lambda / 4n$) epitaxial layers of $\text{Al}_{0.9}\text{Ga}_{0.1}\text{As}$ and $\text{Al}_{0.1}\text{Ga}_{0.9}\text{As}$ create top and bottom mirrors with reflectivity exceeding $99.9\%$, required because the active optical gain length is only a few tens of nanometers.
  2. Quantum Well Active Region: Strained $\text{InGaAs}$ or $\text{GaAs}$ quantum wells emit at $850\text{ nm}$ or $940\text{ nm}$ with direct bandgap internal quantum efficiency $>90\%$.
  3. Oxide Aperture: Wet thermal oxidation at $420^\circ\text{C}$ in steam selectively converts high-aluminum $\text{Al}_{0.98}\text{Ga}_{0.02}\text{As}$ layers into insulating aluminum oxide ($\text{Al}_x\text{O}_y$), confining current and optical modes to a central $4 - 10\,\mu\text{m}$ aperture, slashing threshold current below $1\text{ mA}$.

Gallium Arsenide & VCSEL Engineering Mastery Quiz

Frequently Asked Questions: Gallium Arsenide Wafers

Gallium Arsenide melts at 1,238°C, a temperature at which arsenic exerts an equilibrium sublimation vapor pressure of approximately 1 atm. If unconfined, arsenic boils out of the melt, ruining stoichiometry. A transparent, inert molten boric oxide (B₂O₃) layer floats on top of the molten GaAs while an overpressure of 2 to 5 MPa of argon or nitrogen gas is maintained in the furnace, physically trapping volatile arsenic and ensuring stoichiometric crystal growth.

Liquid Encapsulated Czochralski (LEC) pulls a rotating crystal upward from the melt across steep temperature gradients, creating high thermal stresses that result in etch pit densities (EPD) of 10,000 to 50,000 cm⁻². Vertical Gradient Freeze (VGF) solidifies the melt inside a stationary crucible by slowly translating a low temperature gradient upward. VGF drastically reduces thermal stress, reducing defect densities down to EPD < 1,000 cm⁻², which is critical for VCSEL reliability in AI server clusters.

Semi-Insulating (SI) GaAs is intentionally doped with carbon acceptors to compensate native deep-level donor defects (EL2), achieving ultra-high electrical resistivity (>10⁷ Ω·cm). This provides the dielectric isolation needed for 5G RF power amplifiers (HBTs and pHEMTs) by preventing parasitic capacitive substrate losses. Conductive GaAs is heavily doped with silicon (n-type) or zinc (p-type) to provide low-resistance ohmic bottom contacts for vertical-cavity lasers (VCSELs) and multi-junction solar cells.

GaAs provides an almost perfect lattice match with Aluminum Gallium Arsenide (AlGaAs) across all alloy compositions. This enables epitaxy of multi-layer Distributed Bragg Reflector (DBR) mirrors with over 99.9% reflectivity and wet-oxidized AlAs current apertures. Emitting at 850 nm and 940 nm, GaAs VCSELs achieve high wall-plug efficiency (>50%), circular low-divergence beams for multimode fiber coupling, and low drive currents ideal for 400G and 800G short-reach optical interconnects.

Key capital expenditures include high-pressure VGF crystal growth furnaces, multi-wire diamond slicing saws, chemical-mechanical polishing (CMP) clusters, and cleanroom metrology (X-ray diffraction and surface defect photoluminescence), totaling $65M to $280M. Major operating costs are 6N/7N high-purity gallium and arsenic raw materials, boric oxide consumables, slicing kerf losses, and cleanroom electricity. A standard 6-inch epi-ready GaAs wafer sells for $200 to $600 depending on doping specification and dislocation density.